1. Field of the Invention
This invention relates generally to high speed parallel BIT organized computers and particularly to means for analyzing operating faults in the computers. More particularly, this invention relates to means for evaluating computer operation under malfunctioning dynamic run conditions without extensive probing of hardware.
2. Description of the Prior Art
General purpose high speed computers involve parallel operation of a plurality of data BITS for proper operation. Since correct and reliable operation of the computer requires all of these BITS be at the right logic state at the right time, it is extremely difficult to determine where a fault lies when the computer malfunctions. Prior to the present invention there was no way to evaluate the computer under malfunctioning dynamic run conditions without extensive probing of hardware. Even then, using conventional test equipment, the results were relatively inconclusive as to which computer instruction was malfunctioning, much less which component was at fault. The inconclusive results were due to a lack of capability to know which instructions were being performed and at what time. In other words, there was no timing information directly related to a particular instruction which could be used to initiate a fault analysis procedure.